Power Management Integrated Circuits (PMIC) for Aerospace Applications RFI

The California Institute of Technology’s (Caltech’s) Jet Propulsion Laboratory (JPL), located at 4800 Oak Grove Drive, Pasadena, CA 91109, is issuing the subject RFI to obtain information to assess current industry manufacturing and technical capabilities and receive ROM cost and schedule estimates supporting the development of Power Management IC (PMIC) suitable for NASA space missions. The requested information is for preliminary planning purposes only and does not constitute a commitment, implied or otherwise, that JPL will solicit you for such a procurement in the future. Neither JPL nor the Government will be responsible for any costs incurred by you in furnishing this information. Prospective subcontractors are advised that any information provided shall be deemed to be furnished with unlimited rights to JPL, with JPL assuming no liability for the disclosure, use or reproduction of such data. Please do not include any restrictive data or include restrictive marking. Any information submitted with restrictive marking will not be reviewed and returned. Purpose NASA's Ignition initiative (announced March 24, 2026) and High-Performance Space Computing (HPSC) program represent a fundamental shift toward sustained infrastructure operations with standardized, reusable platforms at continuous cadence. This transition from custom, one-off spacecraft designs to permanent lunar bases, commercial transportation systems, and “Science as a Service” missions drives the need for Power Management Integrated Circuits (PMIC). The purpose of this RFI is to gather information which could eventually lead to an RFP soliciting the development of one or more PMIC optimized for space applications for both commercial industry and government organizations. Overview NASA's Ignition initiative and the High-Performance Space Computing (HPSC) program are driving a strategic shift from traditional one-off spacecraft designs toward standardized, reusable, and sustainable space platforms. These programs emphasize long-duration infrastructure, such as lunar surface operations, commercial cislunar transportation, and persistent science platforms, all of which require reliable, compact, and power-efficient electronics capable of operating in harsh space environments. Power Management Integrated Circuits (PMICs) are critical enablers for these next-generation systems. Highly integrated commercial PMICs currently available provide excellent integration, efficiency, and configurability for terrestrial and airborne applications. However, these devices generally lack the radiation hardness, reliability, and environmental resilience required for NASA missions. Similarly, while some radiation-tolerant power solutions exist, there remains a significant gap in highly integrated, multi-rail, programmable PMICs specifically optimized for modern spacegrade processors, FPGAs, and mixed-signal payloads. This RFI seeks to understand industry capabilities to bridge this gap by developing one or more advanced space-grade PMICs that combine the integration density and flexibility of modern commercial solutions with the radiation performance and mission assurance required for NASA applications. JPL is particularly interested in scalable architectures that can support a wide range of missions, from Low Earth Orbit (LEO) to deep space, while significantly reducing Size, Weight, and Power (SWaP), component count, and overall system complexity. Additional Information Please provide the requested information by August 31, 2026 via email to: JPL Technical Manager, Greg Carr at Gregory.A.Carr@jpl.nasa.gov JPL Acquisition Division personnel, Jane Lee at Jane.Lee@jpl.nasa.gov If you have any questions about this RFI, please contact the undersigned. Sincerely, Jane Lee Group Supervisor, Acquisition Division Office: 818-354-1586 | Mobile: 818-928-9581 4800 Oak Grove Drive Pasadena, CA 91109-8099